1. Field
Example embodiments relate to a circuit designing method. More particularly, example embodiments relate to a method of acquiring an overshoot voltage induced by a voltage stress of an alternate component in a circuit design, and to a method of analyzing a degradation of a gate insulation using the same.
2. Description of the Related Art
Transistors may be subject to stress, e.g., stress caused by voltage applied thereto. When a transistor is subject to stress for a long time, reliability of the transistor may be reduced due to, e.g., a time dependent dielectric breakdown (TDDB) in a gate insulation layer therein. For example, attempts have been made to analyze reliability of a gate insulation layer of a transistor by analyzing degradation of the gate insulation layer as a result of voltage stress thereon via application of a direct current component to the transistor.
However, voltage stress of a direct current (DC) component is not appropriate to verify reliability of the gate insulation layer in a circuit design because the voltage stress of the DC component is simply proportionate to current and resistance and may not reflect different operation conditions of the transistor in various circuits.